To allow signals to travel between different conductive layers in a multilayer printed circuit board PCB, plated via structures are used. Often the plating is done to the whole inner surface of the via, but the plating can also be done selectively at certain parts within the same via to allow for more efficient use of conductive layers in the PCB.
FIGS. 1A and 1B illustrate two examples of selective partitioning of via structures known from prior art.
FIG. 1A illustrates a multilayer PCB 100 with a plurality of conductive layers 101-106 sandwiched with a plurality of dielectric layers 111-113,121-122. FIG. 1A also illustrates a via structure 140 in the PCB 100. The via 140 comprises two plated electrically conductive portions 141 and 142 and between the two plated portions is an electrically isolating portion 145.
FIG. 1B illustrates another multilayer PCB 200 with a plurality of conductive layers 151-156 sandwiched with a plurality of dielectric layers 161-163,171-172 and a via structure 190. The via 190 also comprises two plated conductive portions 191 and 192 but between the two plated portions is an electrically isolating portion 195 that is larger than in FIG. 1A.
The electrically isolated portions 145 and 195 are produced by using plating resist layers 143 and 193 of different thickness.
A disadvantage with using a relatively thin plating resist layer 143 as in FIG. 1A is that the distance between the two plated portions 141 and 142 may be insufficient in order to achieve a valid isolation distance, especially for high voltage electronics.
A disadvantage with a thick plating resist layer 193 as in FIG. 1B is that the manufacturing process is more work intensive as the PCB need a number of additional preparation steps such as milling open portions in the dielectric layers before the thick plating resist layer 193 can be applied.